package NICE_CORE 

import chisel3.util._
trait  SystemConfig{
    val E203_XLEN         = 32
    val E203_ADDR_SIZE    = 32
}

trait Nice_Core_Config{
    val TEXT_SIZE   =   4
    val TEXT_W      =   log2Ceil(TEXT_SIZE)
    val KEY_MAX_SIZE=   8
    val KEY_W       =   log2Ceil(KEY_MAX_SIZE)
}
trait CIM_Config{
    val PUSH_MAX_SIZE = 36
    val PUSH_MAX_SIZE_BITWISE = 144
    val SAVE_MAX_SIZE = 64
    val ROW_MAX = 576
}
